One of the factors characterizing the operating properties of semiconductor memory devices is an AC parameter called tRDL, which relates to the timing of operations in a semiconductor memory device. In particular, the tRDL parameter is closely associated with the number of cycles of a column select line (CSL) signal. The CSL signal selects a column associated with a group of related memory elements. When an ongoing write operation is interrupted, for example, by a row precharge command, while data is being written during cycles of the column select line signal, it may be desirable to wait for a time delay at least equal to the tRDL period in order to ensure that the last data bit is completely written before the row precharge command is processed.
FIG. 1 is a timing diagram illustrating the function of the tRDL parameter.
As shown in FIG. 1, tRDL is a time period from a time point when the last data bit Db3 of a series of data bits (e.g., Db0, Db1, Db2 and Db3) is applied to a bit line in a response to a write command WR to a time point when a row precharge command (RPC) may be processed.
FIG. 2 is a schematic block diagram of a column selection circuit 100 in a conventional semiconductor memory device.
Referring to FIG. 2, a conventional column selection circuit 100 may include a command buffer 22, a column select line enabling unit 24, a column select line disabling unit 25, a column select line driver 26, a PDT generator 27, an IO driver/MUX 28, a bit line sense amplifier 29, and a memory cell MC coupled between a bit line BLUBB and a word line WL.
The command buffer 22 outputs an operation activation signal (e.g. a write activation signal PWAX or a read activation signal PCA) in response to an operation command signal CMD and a clock signal CLK. operation command may be one of a read command, a write command and/or a row precharge command.
Upon receipt of the operation activation signal, the column select line enabling unit 24 outputs a column select line enable signal PCSLE.
Upon receipt of the operation activation signal, the column select line disabling unit 25 generates a column select line disable signal PCSLD in a subsequent clock cycle, which may be, for example, the next clock cycle following the clock cycle in which the column select line enable signal PCSLE was generated.
Under control of the column select line enable signal PCSLE and the column select line disable signal PCSLD, the column select line driver 26 outputs a column select line signal CSL.
The PDT generator 27 receives the column select line signal CSL and responsively generates a PDT signal as an enable signal for the 10 driver/MUX 28.
A transistor TR1 is turned on when the column select line signal CSL is in a high state, and the IO driver/MUX 28 is enabled by the PDT signal, such that data to be written is sensed by the bit line sense amplifier 29 and applied to a bit line BL/BLB. The data is then written to the memory cell MC.
FIG. 3 is a timing diagram showing processes in which the column select line signal CSL of FIG. 2 may be generated.
Referring to FIG. 3, timing waveforms are shown for a clock signal CLK, operation activation signals PWAX and PCA, a column select line enable signal PCSLE, a column select line disable signal PCSLD, and a column select line signal CSL. The command signals WR1, WR2 and RD correspond to the CMD signal of FIG. 2. Specifically, the command signals include write commands WR1 and WR2 and a read command RD.
As shown in FIG. 3, after a write command WR1 is applied in a first clock cycle 1TCK, the write activation signal PWAX is generated in the following cycle of the clock signal CLK as indicated by arrow 51.
The column select line enable signal PCSLE is generated in response to the write activation signal PWAX (arrow 52) which causes the column select line signal CSL to be shifted to a high state (i.e. set) (arrow 53). That is, the column select line signal CSL is set in response to the column select line enable signal PCSLE being activated.
The column select line disable signal PCSLD is generated in response to a second clock cycle 2TCK following the first clock cycle 1TCK (arrow 54). The column select line disable signal PCSLD causes the column select line signal CSL to reset (arrow 55) (i.e., to shift the column select signal CSL to a low state).
Next, in the sequence illustrated in FIG. 3, the write activation signal PWAX is again generated in response to a second write command WR2 applied in the third clock cycle 3TCK, such that the column select line signal CSL is again generated according to the same process as when the first write command WR1 was applied.
A read activation signal PCA is generated in a subsequent clock cycle in response to the read command RD (arrow 56). The read activation signal PCA also causes the column select line enable signal PCSLE to be generated (arrow 57). The column select line signal CSL is again activated in response to the column select line enable signal PCSLE (arrow 58).
The column select line disable signal PCSLD is generated in response to the next clock cycle after the clock cycle in which the read command RD was generated (arrow 59) to inactivate the column select line signal CSL (arrow 60).
If the write activation signal PWAX were generated instead of the read activation signal PCA, i.e., if a write command were applied instead of the read command RD, the column select line signal CSL would be activated or inactivated in the same process, except that the column select line enable signal PCSLE would be generated in response to the write activation signal PWAX.
In the system described above, the column select line signal CSL has a single operational mode in which the column select line signal is activated in response to the column select line enable signal PCSLE in a first clock cycle and is inactivated by the column select line disable signal PCSLD generated in response to the clock cycle following the clock cycle which caused the column select line enable signal PCSLE to be generated.
Therefore, there is a potential problem in that, when a bit line is precharged following a write command, the word line of the memory cell may be disabled after the last data bit to be written to the memory cell is applied to the bit line but before the last data bit is written to the memory cell, such that the last data bit may not be completely written to the memory cell, which may result in loss and/or corruption of data.